Flip chip technology is the fastest growing chip interconnect technology as it allows the largest numbers of inputs/outputs (“I/Os”) for the smallest footprint of the chip. This enables the manufacture of small packages such as packages comprising chip-scale packages.
The use of flip chip bump technology also extends to passive filters, detector arrays and MEMS devices. IBM introduced this technology in the early 1960's with the solid logic technology in the IBM System/360™. It extended interconnection capabilities beyond existing wire-bonding techniques, allowing the area array solder-bump configuration to extend over the entire surface of the chip (die) providing solder bumps for interconnection to a substrate by the C4. This allowed for the highest possible I/O counts to meet the increasing demand for electrical functionality and reliability in IC technology.
The original wafer-bumping process of metal mask evaporation (UBM) involve the evaporation onto a wafer surface of solder through mask openings in an area array fashion. The need for increased I/O density and count, and pressures to lower the cost of flip-chip interconnections have spurred the development of other wafer bumping techniques such as electroplating or stencil-printing/paste-screening (solder paste) bump processes. Some of the more newly developed bumping processes include transfer printing, solder jetting, and bumpless and conductive particle applications.
In its broader aspect UBM comprises the application of a metal coating to the die contact pads such as aluminum or copper contact pads, where the metal coating provides a surface that can adhere to solder. The UBM typically consist of an adhesion layer, such as Ti or TiW and a barrier layer, such as Ni, to which the solder gets attached.
The overview of flip chip technology shows its major advantage lies in utilizing the total chip area to make the I/O connections, whereas wire bonding uses only the chip periphery. A disadvantage of flip chip technology is that stresses that arise from the thermal mismatch between the silicon (chip) thermal expansion coefficient (“CTE”) and the CTE of the substrate are borne fully by the solder bumps (“C4s”) used to make the interconnect between chip and substrate.
The so-called “solder bumps” provide a space between the chip and the substrate, usually filled in the last steps of the assembly process with a nonconductive “underfill” material that adhesively joins the entire surface of the chip or die to the substrate. The underfill not only blocks contaminants from entering into the structure but also locks the chip or die to the organic substrate so that differences in thermal expansion do not break or damage the electrical connections of the bumps
Government regulations and customer needs have also impacted flip-chip interconnection technology requiring manufacturers to make a major transition from Pb/Sn to Pb-free solders and to produce larger wafers. Two main interconnection problems have surfaced during the transition of leaded to Pb-free solders; electromigration (“EM”) and chip package interactions (“CPI”). The principal CPI problem comprises semiconductor dielectric cracks due to the high stresses, known as white bump, which resulted when the industry changed over to the use of harder lead-free solders. Presently, the solution to the problems of these two technologies (EM and CPI) are counter to each other, i.e., solder additives and grain orientation which enhance EM performance tend to harden the solder even more, resulting in increased CPI stresses and white bumps. Additionally, the current FBEOL structure tends to localize the current flow by not allowing a good thick conductive metal to distribute the current around via openings in the circuit produced lithographically, such as by the use of photo sensitive polyimides (“PSPI”).